Continued innovations in semiconductor process technologies are enabling higher integration densities and device scaling. As the semiconductor industry moves towards the 7-nm technology node and beyond, semiconductor FET device structures must be scaled to smaller dimensions to provide increased device width per footprint area. In this regard, non-planar FET devices such as nanosheet FET devices, nanowire FET devices, vertical FET devices, FinFET devices, etc., are a viable option for continued CMOS scaling. In general, a nanowire FET device comprises a device channel which comprises one or more nanowire layers in a stacked configuration, wherein each nanowire comprises an elongated semiconductor layer that has a width which is substantially the same or slightly larger than a thickness of the elongated semiconductor layer. A nanosheet FET device is similar to a nanowire FET device sheet in that a device channel comprises one or more nanosheet layers in a stacked configuration, but wherein each nanosheet layer has a width which is substantially greater than a thickness of the nanosheet layer. In nanowire/nanosheet FET devices, a common gate structure is formed above and below each nanowire/nanosheet layer in the stacked configuration, thereby increasing the FET device width (or channel width), and thus the drive current, for a given footprint area.
The threshold voltage (Vt) of a FET device is the voltage that is required to turn the transistor on. Multi-threshold voltage CMOS (MTCMOS) technologies implement methods for fabricating FET devices with multiple threshold voltages in order to optimize device performance (delay, power, etc.) for different applications. The threshold voltage of a FET device can be tuned using various techniques. For example, the threshold voltage of an FET device varies with gate dielectric thickness, wherein the threshold voltage decreases as the thickness of gate dielectric layer decreases. In addition, multi-Vt fabrication methods can tune the threshold voltages of non-planar FET devices by changing the thickness and/or material composition of work function metal (WFM) layers that are formed as part of high-k gate dielectric/metal gate (HKMG) structures for the non-planar FET devices such as nanosheet FET devices. The material composition of the work function metal layers can be modified through dopant implantation, or by forming multilayer WFM structures comprising stacks of two or more different types of work function metal layers.
The HKMG structures for p-type FET devices and n-type FET devices are typically formed with different WFM layers (one for p-FETs and one for n-FETs) as a way to optimize or otherwise tune the threshold voltages of the n-FETs and p-FETs, without the need for channel doping to achieve Vt tuning. In addition, the threshold voltages of n-type FET devices in different device regions can be tuned by using different metallic composition and/or layers for work function metal layers for the n-type FET devices. Similarly, the threshold voltages of p-type FET devices in different device regions can be tuned by using different metallic composition and/or layers for work function metal layers for the p-type FET devices. In this regard, WFM patterning methods are widely used in the semiconductor industry to fabricate FET devices with different work function metal layers so as to realize FET devices with multiple threshold voltages. However, the WFM patterning process can result in the formation of interfacial oxide layers (or increase the thickness of existing interfacial oxide layers) on active silicon channel layer of the FET devices as a result of etching environments used for the WFM patterning. The unwanted growth (or regrowth) of interfacial oxide layers on silicon channel layers of FET devices results in non-uniformity of the channel layers of the FET devices, as well as degraded device performance.